Nano-CMOS circuit and physical design /

Nano-CMOS circuit and physical design /

Based on the authors' expansive collection of notes taken over the years, Nano-CMOS Circuit and Physical Design bridges the gap between physical and circuit design and fabrication processing, manufacturability, and yield. This innovative book covers: process technology, including sub-wavelength...

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Bibliographic Details
Other Authors: Wong, Ban P., 1953-
Format: Electronic eBook
Language:English
Published: Hoboken, N.J. : John Wiley, ©2005.
Subjects:
Metal oxide semiconductors, Complementary > Design and construction.
Integrated circuits > Design and construction.
Online Access:CONNECT
Table of Contents:
  • COVER
  • TABLE OF CONTENTS
  • FOREWORD
  • PREFACE
  • CHAPTER 1 NANO-CMOS SCALING PROBLEMS AND IMPLICATIONS
  • 1.1 Design Methodology in the Nano-CMOS Era
  • 1.2 Innovations Needed to Continue Performance Scaling
  • 1.3 Overview of Sub-100-nm Scaling Challenges and Subwavelength Optical Lithography
  • 1.3.1 Back-End-of-Line Challenges (Metallization)
  • 1.3.2 Front-End-of-Line Challenges (Transistors)
  • 1.4 Process Control and Reliability
  • 1.5 Lithographic Issues and Mask Data Explosion
  • 1.6 New Breed of Circuit and Physical Design Engineers
  • 1.7 Modeling Challenges
  • 1.8 Need for Design Methodology Changes
  • 1.9 Summary
  • References
  • PART I PROCESS TECHNOLOGY AND SUBWAVELENGTH OPTICAL LITHOGRAPHY: PHYSICS, THEORY OF OPERATION, ISSUES, AND SOLUTIONS
  • CHAPTER 2 CMOS DEVICE AND PROCESS TECHNOLOGY
  • 2.1 Equipment Requirements for Front-End Processing
  • 2.2 Front-End-Device Problems in CMOS Scaling
  • 2.3 Back-End-of-Line Technology
  • References
  • CHAPTER 3 THEORY AND PRACTICALITIES OF SUBWAVELENGTH OPTICAL LITHOGRAPHY
  • 3.1 Introduction and Simple Imaging Theory
  • 3.2 Challenges for the 100-nm Node
  • 3.3 Resolution Enhancement Techniques: Physics
  • 3.4 Physical Design Style Impact on RET and OPC Complexity
  • 3.5 The Road Ahead: Future Lithographic Technologies
  • References
  • PART II PROCESS SCALING IMPACT ON DESIGN
  • CHAPTER 4 MIXED-SIGNAL CIRCUIT DESIGN
  • 4.1 Introduction
  • 4.2 Design Considerations
  • 4.3 Device Modeling
  • 4.4 Passive Components
  • 4.5 Design Methodology
  • 4.6 Low-Voltage Techniques
  • 4.7 Design Procedures
  • 4.8 Electrostatic Discharge Protection
  • 4.9 Noise Isolation
  • 4.10 Decoupling
  • 4.11 Power Busing
  • 4.12 Integration Problems
  • 4.13 Summary
  • References
  • CHAPTER 5 ELECTROSTATIC DISCHARGE PROTECTION DESIGN
  • 5.1 Introduction
  • 5.2 ESD Standards and Models
  • 5.3 ESD Protection Design
  • 5.4 Low-C ESD Protection Design for High-Speed I/O
  • 5.5 ESD Protection Design for Mixed-Voltage I/O
  • 5.6 SCR Devices for ESD Protection
  • 5.7 Summary
  • References
  • CHAPTER 6 INPUT/OUTPUT DESIGN
  • 6.1 Introduction
  • 6.2 I/O Standards
  • 6.3 Signal Transfer
  • 6.4 ESD Protection
  • 6.5 I/O Switching Noise
  • 6.6 Termination
  • 6.7 Impedance Matching
  • 6.8 Preemphasis
  • 6.9 Equalization
  • 6.10 Conclusion
  • References
  • CHAPTER 7 DRAM
  • 7.1 Introduction
  • 7.2 DRAM Basics
  • 7.3 Scaling the Capacitor
  • 7.4 Scaling the Array Transistor
  • 7.5 Scaling the Sense Amplifier
  • 7.6 Summary
  • References
  • CHAPTER 8 SIGNAL INTEGRITY PROBLEMS IN ON-CHIP INTERCONNECTS
  • 8.1 Introduction
  • 8.2 Interconnect Parasitics Extraction
  • 8.3 Signal Integrity Analysis
  • 8.4 Design Solutions for Signal Integrity
  • 8.5 Summary
  • References
  • CHAPTER 9 ULTRALOW POWER CIRCUIT DESIGN
  • 9.1 Introduction
  • 9.2 Design-Time Low-Power Techniques
  • 9.3 Run-Time Low-Power Techniques
  • 9.4 Technology Innovations for Low-Power Design
  • 9.5 Perspectives for Future Ultralow-Power Design
  • References
  • PART III IMPA.

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